As described in U.S. Pat. No. 4,688,223 issued to Motika and Waicukauski and incorporated herein by reference, complex large scale integrated circuit devices fabricated on a single semiconductor chip contain thousands of functional circuit elements which are inaccessable for discrete testing. Because of the complexity of the internal interconnections and their combinational interdependencies, testing for device integrity becomes even more time consuming as the number of individual components on the die increases. Recently, as the number of circuit elements increases from thousands to hundreds of thousands, the amount of time and storage necessary in testing such components increases even more dramatically than described in the above-identified patent.
Integrated circuits of such complexity are known to be tested by applying a test pattern of logic signals to the inputs to these circuits. The test pattern consists of "1"s and "0"s, with the frequency of occurrence of the "1"s or "0"s on a given primary input being determined by a so-called weighting factor.
As used herein, weighting refers to controlling the relative frequency of "1s" and "0s" in a random sequence of logic signals used to test digital circuits. Thus, for purposes of the present discussion, weighting defines the frequency of the "1" values in this sequence compared to the frequency of the "0" values. A weighting of 9/10 means that 9 "1s" are produced to every "0" produced. When the frequency of "1s" equals the frequency of "0s", the sequence is called non-weighted or uniformly distributed.
Weighting as applied to pseudo-random number generation is expressed in terms of the probability that in a given pattern a "1" or a "0" will be generated. This may be expressed in terms of a ratio or percentage.
As described in the Motika et al. patent, weighting is dependent upon the number of circuit elements in the circuit to be tested, and more particularly the number of inputs to these devices. Thus, for larger and larger numbers of circuit elements, since the weighting factor is proportioned to the number of inputs which is limited, the calculated weights become very close to uniform distribution weights. Thus there is a considerable increase in the numbers of patterns required to appropriately test the VLSI circuits in question.
In general, testing requires the delivery of certain values, "1"s or "0"s, to the circuit and detecting the response of the circuit. In a so-called random test system, random numbers, not a calculated pattern, are applied to the circuit in order to test all the various states. However, such completely random number generation for testing of circuits is simply impossible to implement due to the numbers of combinations of "1"s and "0"s which would adequately test the circuit.
The problem with completely random number generation is that there may be circuit elements which will not be tested. This is because exercising these elements requires the coincidence of a large number of random events which will not occur within a practical amount of time.
To overcome this, systems have been developed that change the probabilities for the generation of "1s" or "0s" in the random input signals in such a way that the necessary coincidence happens more frequently. This is done by using a weighted random number generator. By techniques that are well known, a particular weight causes more frequent generation of "1s" or "0s" on a given primary input as necessary for exercising the particular circuit.
The problem with this approach is that many circuits impose conflicting requirements for testing their circuit elements. Thus one element may require a large number of "1s" at a given primary input, where another element may require a larger number of "0s".
The Motika et al. patent does not address this issue but rather averages for conflicting requirements. As a result, this system does not permit testing many potential faults.
More particularly, and by way of further background, testing of digital circuits with randomly generated patterns of "1s" and "0s" for random testing purposes is considered to be an attractive alternative to deterministic methods using stored test patterns, each of which are used to detect a fault in the circuit such as a line stuck at either "0" or "1" regardless of the input signals to the corresponding device. Studies of such methods both in the external and the built-in test environment show several major advantages of random testing. Firstly, it allows significant compaction of test data which is especially important for built-in self-test. Secondly, random testing provides cost-effective means of increasing the coverage of faults not explicitly targeted during deterministic test generation.
In order to successfully use random testing techniques one has to address several problems. The most important of them is achieving an acceptable level of fault coverage for a targeted set of faults, usually single stuck-at faults. Several techniques for probabilistic fault coverage estimation have been developed as described by E. J. McClusky, S. Makar, S. Mourad and K. D. Wagner, in a paper entitled Probability Models for Pseudorandom Test Sequences in the Proceedings of the International Test Conference, 1987, p.p. 471-479. Also, advances in fault simulation technology made it possible to quickly evaluate fault coverage of long random test sequences as described in an article by J. Waicukauski and E. Lindbloom entitled Fault Detection Effectiveness of Weighted Random Patterns, in the Proceedings of International Test Conference, 1988, pp. 245-249.
Studies done using these techniques show fault coverage obtainable with the use of uniformly distributed random test patterns to be unacceptably low. It was observed that most practical as well as benchmark circuits contain so called random pattern resistant structures that are very hard to test using uniformly distributed random sequences. An example of such a structure is an n-input AND gate, for which the probability of detecting stuck-at-one faults at the inputs as well as stuck-at-zero fault at the output falls exponentially with the growth of n.
This observation prompted an improvement to the random testing methods where non-uniform probability distributions of test patterns were used and proved to be effective in numerous cases. This is described by P. Bardell, W. McAnney and J. Savir in a book entitled Built-In Test for VLSI, in Pseudorandom Techniques. John Wilkey & Sons, New York, 1987, 354 p. Random testing with non-uniform input signal distribution is called weighted random testing and the probabilities of input signals being equal to 1 are known as input weights.
Several procedures have been developed for calculating optimal weights and are described in the above book by P. Bardell, W. McAnney and J. Savir; by J. Waicukauski, E. Lindbloom, E. Eichelberger and O. Forlenza in an article entitled A Method for Generating Weighted Random Test Patterns, in the IBM Journal of Research and Development, vol. 33, No. 2, March 1989, pp. 149-161; by V. D. Agrawal in an article entitled An Information Theoretic Approach to Digital Fault Testing in the IEEE Transactions on Computers, vol. C-30, August 1981, pp. 582-587; by R. Lisanke, F. Brglez and A. Degeus in an article entitled Testability-Driven Random Test-Pattern Generation in the IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 6, November 1987, pp. 1082-1087; by H. Wunderlich in an article entitled PROTEST: A Tool for Probabilistic Testability Analysis in the Proceedings of Design Automation Conference, 1985, pp. 204-211; and again by H. Wunderlich in an article entitled On Computing Optimized Input Probabilities for Random Tests published in the Proceedings of Design Automation Conference, 1987, pp. 392-398. Some of the above systems are heuristic, based on circuit structure analysis. Others are based on analytical calculation of fault detection probabilities and use optimization, hill climbing, techniques to reach a maximum of these probabilities in the n-dimensional space of input weights. Attempts were also made to obtain optimal weights by randomizing the set of functional test vectors for a circuit as described in an article by F. Siavoshi entitled WTPGA: A Novel Weighted Test-Pattern Generation Approach for VLSI Built-In Self Test in the Proceedings of International Test Conference, 1988, pp. 256-262. For many circuits the results of weighted random testing are significantly better than those obtained with uniformly random tests both in terms of fault coverage and test length. However, as described by E. Eichelberger, E. Lindbloom, J. Waicukauski and T. Williams in a book entitled Structured Logic Testing, published by Prentice Hall, Englewood Cliffs, N.J., 1991, 183 p., it was further observed that some structures in logic circuits are resistant even to weighted random testing. The classical example of such a structure is n-input AND gate and an n-input OR gate which have their corresponding inputs connected. Obviously, detecting faults at the terminals of the AND gate require the values of input weights to be different from those necessary for the OR gate. Averaging on these requirements as suggested by the known weight calculation techniques will produce patterns with a uniform distribution which have been proven ineffective for both gates.
Based on this experience, it was conjectured that high fault coverage can only be obtained by weighted random tests using multiple sets of weights.
The basic idea underlying efforts to calculate multiple weight sets is of partitioning the fault set into subsets that can be covered by a single vector of weights. As described by H. Wunderlich in an article entitled Multiple Distributions for Biased Random Test Patterns published in the IEEE Transactions on Computer-Aided Design, vol. 9, No. 6, June 1990, pp. 584-593, Wunderlich partitions the fault set explicitly by including each fault into one of the partitions in a way that maximizes a cost function based on the gradient of detection probability. The method is expensive computationally and it is only as accurate as the fault detection probability estimation algorithm which is used in these calculations. However, it is known that the exact detection probability calculation problem is NP-complete. Also estimation algorithms which achieve a given level of accuracy in polynomial time can not be built.
A completely different approach to the partitioning problem described is based on the observation that the faults which require similar input weights to improve their detectability are often grouped within the same structural partitions of the circuit under test. Although this observation was first made by Waicukauski et al. as described in the above article, the WRP method introduced there tries to create approximately equal level of switching activity throughout the circuit and fails to concentrate on subcircuits with undetected faults in them.
It will be appreciated that weighted random test pattern generation has been utilized for a considerable time in the testing of complex circuitry primarily in large scale integration. For reference, such a system is described in U.S. Pat. No. 3,719,885 issued to Robert Gordon Carpenter et al. on Mar. 6, 1973 and incorporated herein by reference.